Scalable register bypassing for FPGA-based processors
نویسندگان
چکیده
منابع مشابه
Scalable register bypassing for FPGA-based processors
In this paper, a scalable scheme, configurable via register-transfer level parameters, for full register bypassing in a modern embedded processor architecture, termed ByoRISC, is presented. The register bypassing specification is parameterized regarding the number of homogeneous register file read and write ports and the number of pipeline stages of the processor. The performance characteristic...
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ژورنال
عنوان ژورنال: Microprocessors and Microsystems
سال: 2009
ISSN: 0141-9331
DOI: 10.1016/j.micpro.2009.07.002